• M. KHETATBA Dept d’informatique, Université d’Annaba
  • R. BOUDOUR Dept d’informatique, Université d’Annaba


System-on-Chip  (SoC) designs are increasingly becoming more complex. One of the major constraints is the time to market
New design methods are necessary, and the tendency is with the integration of the software and hardware parts on the same
chip.  Efficient on-chip communication architectures are critical for achieving desired performance in these systems  Thus, the
development of codesign’s modern methods and  the appearance of hardware description languages  (HDL) based on C/C++
such as SystemC or specC allowing to employ the same language to describe the software and the hardware, and returning of
this fact easier and more effective Co-simulation. These methods would be able to generate an optimal solution starting from a
functional specification by reducing the time and the cost of the design. Thus, one of the main objectives of this paper is the
development  of  a SystemC  platform  for multiprocessors architectural exploration at  the compromise  level  (TLM) by using
SystemC/TLM.  It must  lead  to partition  system  into hw/sw and also  to validate  it by simulation or  to move easily modules
from hardware to software (or vice versa) during the architectural exploration. Except for the software task priorities that could
be modified, we only need to recompile and simulate




Construction de filtres pour le traitement d’images numériques
[7] J. Chevalier, O. Benny, M. Rondonneau, G. Bois, M.
Aboulhamid, F.-R. Boyer, “SPACE: A
Hardware/Software SystemC modeling platform
including an RTOS," Forum on specification and
Design Languages, 2003.
[8] G. Nicolescu et al., “Validation in a Component-Based
Design Flow for Multicore SoCs”. Proc. 15th Int’l
Symp.System Synthesis (ISSS 02), ACM Press, pp.
162-167, 2002
[9] M. Loghi, M. Poncino, and L. Benini. Cycle-accurate
power analysis for multiprocessor systems-on-a-chip.
In Proceedins of the 14th ACM Great Lakes
symposium on VLSI, pages 410–406. ACM Press,
[10] M. Loghi, F. Angiolini, D. Bertozzi, L. Benini, and R.
Zafalon. Analyzing on-chip communication in a
mpsoc environment. In Proceedings of the conference
on Design, automation and test in Europe, page 20752.
IEEE Computer Society, 2004.
[11] F. Petrot, D. Hommais, and A. Greiner. "Cycle precise
core based hardware/software system simulation with
predictable event propagation". In Proc. of the 23rd
Euromicro Conf., pages 182 -187, Hungary, Sep.
[12] A. Donlin. Transaction level modeling: Flows and use
models. In A. Press, editor, CODES+ISSS ’04:
Proceedings of the 2nd IEEE/ACM/IFIP International
Conference on Hard-ware/software Codesign and
System Synthesis, pages 75–80, New York, NY, 2004.
[13] F. Ghenassia. Transaction-Level Modeling with
SystemC:TLM Concepts and Applications for
Embedded Systems.Springer, November 2005
[14] L. Cai and D. Gajski, Transaction level modeling: an
overview, Proc. Intl. Conf. Hardware/Software
Codesign and System Synthesis, October 2003, pp.
[15] J. Colgan and P. Hardee, Advancing Transaction Level
Modeling – Linking the OSCI and OCP-IP Worlds at
Transaction Level,Open-Systems Publishing
(November 6, 2006); www.opensystems-
[16] T. Kogel, A.Haverinen, andJ. Aldis, OCPTLMfor
Architectural Modeling. Methodology: White Paper,
OCP-IP (November 6, 2006);
[17] N. Calazans, E. Moreno, F. Hessel, V. Rosa, F.
Moraes, and E. Carara, From VHDLregister transfer
level to SystemC transaction level modeling: a
comprehensive case study, Proc. Symp. Integrated
Circuits and Systems, September 2003, pp. 355–360.
[18] Cadence NCSystemC.
[19] CoCentric System Studio.
[20] CoWare.
[21] F. Vahid, D.D. Gajski, Closeness metrics for system-
level functional partitioning. O-8186-7156-4/95 IEEE,
[22] B. Knerr, M. Holzer, M. Rupp, HW/SW Partitioning
Using High Level Metrics. Copyright International
Institute of Informatics and Systems, published in the
proceedings of the International Conference on
Computing, Communications and Control
Technologies (CCCT), pp. 33-38, Austin, 2004[1] T. Groetker, S. Liao, G. Martin, S. Swan, System
Design with SystemC. Kluwer Academic Publishers,
[2] M. Besana, M. Borgatti, Application Mapping to a
Hardware Platform through Automated Code
Generation Targeting a RTOS: A Design Case Study.
pages 41–44.Proc. of DATE Conference and
Exhibition Design Forum, March 2003
[3] J. Staunstrup, W. Wolf, Hardware/Software Co-
Design, Principles and Practice. Kluwer Academic
Publishers, 1997
[4] OSCI. SystemC.
[5] D. D. Gajski, J. Zhu, R. D¨omer, A. Gerstlauer, S.
Zhao, SpecC: Specification Language and Design
Methodology. Kluwer Academic Publishers, 2000
[6] F. Fummi, S. Martini, G. Perbellini, M. Poncino,
“Native ISS SystemC integration for the Co-simulation
of multi-processor SoC," DATE 2004, Vol. 1, pp. 564-
Comment citer
KHETATBA, M.; BOUDOUR, R.. SIMULATION PLATFORM IN TLM OF SYSTEM ON CHIP USING RETARGETABLE ISS. Courrier du Savoir, [S.l.], v. 14, mai 2014. ISSN 1112-3338. Disponible à l'adresse : >>. Date de consultation : 15 jui. 2020