SIMULATION PLATFORM IN TLM OF SYSTEM ON CHIP USING RETARGETABLE ISS
System-on-Chip (SoC) designs are increasingly becoming more complex. One of the major constraints is the time to market
New design methods are necessary, and the tendency is with the integration of the software and hardware parts on the same
chip. Efficient on-chip communication architectures are critical for achieving desired performance in these systems Thus, the
development of codesign’s modern methods and the appearance of hardware description languages (HDL) based on C/C++
such as SystemC or specC allowing to employ the same language to describe the software and the hardware, and returning of
this fact easier and more effective Co-simulation. These methods would be able to generate an optimal solution starting from a
functional specification by reducing the time and the cost of the design. Thus, one of the main objectives of this paper is the
development of a SystemC platform for multiprocessors architectural exploration at the compromise level (TLM) by using
SystemC/TLM. It must lead to partition system into hw/sw and also to validate it by simulation or to move easily modules
from hardware to software (or vice versa) during the architectural exploration. Except for the software task priorities that could
be modified, we only need to recompile and simulate
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