MEMORY REQUIREMENTS FOR HARDWARE IMPLEMENTATION OF THE H.264 ENCODER MODULES
Résumé
For a hardware implementation of any image processing algorithm, it is necessary to study the input/output of each processingmodule even before studying the internal architecture of these modules. And that to prepare a simulation platform, with
internal and external memory, necessary to load and to prepare the input for the modules. These memories are also used as
intermediate component between the different modules to provide the possibility of parallelism. In this work we give the
architecture of internal and external memory used by the H.264 encoder in order to develop a simulation platform for
processing modules. This platform can be realized in FPGA platform chosen according to the memory requirements.
Références
[1] ISO/IEC 14496–10:2003, “Coding of Audiovisual
Objects-Part 10: Advanced Video Coding,” 2003,
also ITU-T Recommendation H.264 “Advanced video
coding for generic audiovisual services”.
[2] K. Babionitakis, G. Doumenis, G. Georgakarakos, G.
Lentaris, K. Nakos, D. Reisis, I. Sifnaios, and N.
Vlassopoulos, “A real-time H.264/AVC VLSI
encoder architecture,” Springer, Real-Time Image
Proc, pp.43–59, 2009.
[3] K. Messaoudi, S. Toumi, E. Bourennane, “Material
architecture proposition for the block matching
method of motion estimate in H264 standard,”
ICTTA’08, Damascus, Syria, Jul. 2008.
[4] K. Messaoudi, S. Toumi, E. Bourennane, “Proposal
and study for an architecture hardware/software for
the implementation of the standard H264,” CISA’08,
Mediterranean Conference on Intelligent Systems and
Automation- Proceeding editor AIP (American
Institute of Physics), Annaba-Algeria, jun. 2008.
[5] J. Ostermann, J. Bormans, P. List, D. Marpe, M.
Narroschke, F. Pereira, T. Stockhammer, and T.
Wedi, “Video coding with H.264/AVC: Tools,
Performance, and Complexity,” IEEE, Circuits and
Systems Magazine, pp. 7-28, First Quarter 2004.
[6] T. Chen, C. Lian and L. Chen, “Hardware
Architecture Design of an H.264/AVC Video Codec,”
IEEE – 7D-3, pp. 750-757, 2006.
[7] I. E. G. Richardson, “H.264 and MPEG-4 Video
Compression,” 2003, The Robert Gordon University,
Aberdeen, UK, WILEY edition 2003.
Objects-Part 10: Advanced Video Coding,” 2003,
also ITU-T Recommendation H.264 “Advanced video
coding for generic audiovisual services”.
[2] K. Babionitakis, G. Doumenis, G. Georgakarakos, G.
Lentaris, K. Nakos, D. Reisis, I. Sifnaios, and N.
Vlassopoulos, “A real-time H.264/AVC VLSI
encoder architecture,” Springer, Real-Time Image
Proc, pp.43–59, 2009.
[3] K. Messaoudi, S. Toumi, E. Bourennane, “Material
architecture proposition for the block matching
method of motion estimate in H264 standard,”
ICTTA’08, Damascus, Syria, Jul. 2008.
[4] K. Messaoudi, S. Toumi, E. Bourennane, “Proposal
and study for an architecture hardware/software for
the implementation of the standard H264,” CISA’08,
Mediterranean Conference on Intelligent Systems and
Automation- Proceeding editor AIP (American
Institute of Physics), Annaba-Algeria, jun. 2008.
[5] J. Ostermann, J. Bormans, P. List, D. Marpe, M.
Narroschke, F. Pereira, T. Stockhammer, and T.
Wedi, “Video coding with H.264/AVC: Tools,
Performance, and Complexity,” IEEE, Circuits and
Systems Magazine, pp. 7-28, First Quarter 2004.
[6] T. Chen, C. Lian and L. Chen, “Hardware
Architecture Design of an H.264/AVC Video Codec,”
IEEE – 7D-3, pp. 750-757, 2006.
[7] I. E. G. Richardson, “H.264 and MPEG-4 Video
Compression,” 2003, The Robert Gordon University,
Aberdeen, UK, WILEY edition 2003.
Comment citer
MESSAOUDI, KAMEL. et al.
MEMORY REQUIREMENTS FOR HARDWARE IMPLEMENTATION OF THE H.264 ENCODER MODULES.
Courrier du Savoir, [S.l.], v. 14, mai 2014.
ISSN 1112-3338.
Disponible à l'adresse : >https://revues.univ-biskra.dz/index.php/cds/article/view/416>. Date de consultation : 22 déc. 2024
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